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NXP Semiconductors /LPC15xx /SCT2 /DMAREQ0

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Interpret as DMAREQ0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DEV_00RESERVED0 (DRL0)DRL0 0 (DRQ0)DRQ0

Description

SCT DMA request 0 register

Fields

DEV_0

If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,…, event 15 = bit 15).
RESERVED

Reserved
DRL0

A 1 in this bit makes the SCT set DMA request 0 when it loads the Match_L/Unified registers from the Reload_L/Unified registers.
DRQ0

This read-only bit indicates the state of DMA Request 0

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data